Transistors such as metal oxide semiconductor field effect transistors (MOSFETs) or simply field effect transistors (FETs) or MOS transistors are the core building blocks of the vast majority of semiconductor integrated circuits (ICs). A FET includes source and drain regions between which a current can flow through a channel under the influence of a bias applied to a gate electrode that overlies the channel. Some semiconductor ICs, such as high performance microprocessors, can include millions of FETs. For such ICs, decreasing transistor size and thus increasing transistor density has traditionally been a high priority in the semiconductor manufacturing industry. Transistor performance, however, must be maintained even as the transistor size decreases.
A FINFET is a type of transistor that lends itself to the goals of reducing transistor size while maintaining transistor performance. The FINFET is a non-planar, three dimensional transistor formed in a thin fin that extends upwardly from a semiconductor substrate. The semiconductor substrate may be a bulk silicon wafer from which the fin structures are formed or may be a silicon-on-insulator (SOI) wafer disposed on a support substrate. The SOI wafer includes a silicon oxide layer and a silicon-containing material layer overlying the silicon oxide layer. The fin structures are formed from the silicon-containing material layer. The fin structures are typically formed using conventional photolithographic or anisotropic etching processes (e.g., reactive ion etching (RIE) or the like).
Electrical isolation of the fin structures is necessary to avoid electromechanical interference (EMI) and/or parasitic leakage paths between the various devices. Isolating fin structures on a bulk silicon wafer is especially problematic as the silicon of the bulk silicon wafer between the fin structures forms a conductive path. Shallow trench isolation (STI) is a technique used to electrically isolate transistors or electrical devices. Typically, STI is created during a relatively early fabrication stage(s), before the transistors are formed. A conventional STI process for FinFET devices involves creating isolation trenches in the semiconductor substrate through an anisotropic etch process. The isolation trench between each adjacent fin structures has a relatively high aspect ratio (e.g., ratio of the depth of the isolation trench to its width). A dielectric filler material, such as silicon oxide, is deposited into the isolation trenches, for example, using an enhanced high aspect ratio process (eHARP) to fill the isolation trenches. The deposited dielectric material may then be polished by a chemical-mechanical polishing (CMP) process that removes the excess dielectric material and creates a planar STI structure. The planarized oxide is etched back to form a partially recessed uniformly thick oxide isolation between the fin structures and to expose the upper vertical sidewalls of the fins for further processing. Unfortunately, the dielectric filler material deposited via eHARP is not entirely resilient to various etching and/or cleaning processes or the like and may be further etched and/or recessed during subsequent downstream processing, resulting in leakage current issues, poor isolation, and the like.
Accordingly, it is desirable to provide integrated circuits including FINFET devices with shallow trench isolation (STI) that includes a dielectric fill that is more resilient to downstream processing. In addition, it is to serve all to provide methods for fabricating such integrated circuits. Furthermore, other desirable features and characteristics of the present invention will become apparent from the subsequent detailed description and the appended claims, taken in conjunction with the accompanying drawings and this background.